View MX26L1620XAI-12_1645171.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 16m-bit [1m x 16] cmos multiple-time-programmable eprom advanced information features ? 1,048,576 x 16 byte structure ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? low vcc write inhibit is equal to or less than 2.5v ? compatible with jedec standard ? high performance - fast access time: 90/120ns (typ.) - fast program time: 35s/chip (typ.) - fast erase time: 45s/chip (typ.) ? low power consumption - low active read current: 10ma (typ.) at 5mhz - low standby current: 30ua (typ.) ? minimum 100 erase/program cycle ? 10-year data retention ? status reply - data polling & toggle bits provide detection of program and erase operation completion ? 12v acc input pin provides accelerated program capability ? output voltages and input voltages on the device is determined by the voltage on the vi/o pin. - vi/o voltage range:1.65v~3.6v ? package - 44-pin sop - 48-pin tsop - 48-ball csp general description the mx26l1620 is a 16m bit mtp eprom tm organized as 1m bytes of 16 bits. mxic's mtp eprom tm offer the most cost-effective and reliable read/write non-volatile random access memory. the mx26l1620 is packaged in 44-pin sop, 48-pin tsop and 48-ball csp. it is designed to be reprogrammed and erased in system or in standard eprom programmers. the standard mx26l1620 offers access time as fast as 90ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention, the mx26l1620 has separate chip enable (ce) and output enable oe controls. mxic's mtp eprom tm augment eprom functionality with in-circuit electrical erasure and programming. the mx26l1620 uses a command register to manage this functionality. mxic's mtp eprom tm technology reliably stores memory contents even after 100 erase and program cycles. the mxic cell is designed to optimize the erase and program mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and programming operations produces reliable cycling. the mx26l1620 uses a 2.7v to 3.6v vcc supply to perform the high reliability erase and auto program/ erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epiprocess. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc +1v.
2 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 pin configuration 48 csp 1. ball pitch=0.75mm for mx26l1620xa (top view, ball down) a13 a b c d e f 12345678 a14 a15 a16 v i/o gnd a11 a10 a12 q14 q15 q7 a8 we a9 q5 q6 q13 acc reset nc q11 q12 q4 nc a18 nc q2 q3 vcc a19 a7 a17 a6 q8 q9 q10 a5 a3 ce q0 q1 a4 a2 a1 a0 gnd oe 8.0 mm 7.0 mm 2. ball pitch=0.8mm for mx26l1620xb(top view, ball down) a13 6 5 4 3 2 1 abcdefgh a9 we nc a7 a3 a12 a8 acc a17 a4 a14 a10 nc a18 a6 a2 a15 a11 a16 reset a19 nc a5 a1 v i/o q7 q5 q2 q0 a0 q15 q14 q12 q10 q8 ce q13 vcc q11 q9 oe gnd q6 q4 q3 q1 gnd 8.0 mm 7.0 mm
3 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 symbol pin name a0~a19 address input q0~q15 data inputs/outputs ce chip enable input we write enable input oe output enable input reset hardware reset pin, active low vcc +3.0v single power supply acc hardware acceleration pin v i/o i/o power supply (for 48 tsop and 48 csp package only) gnd device ground nc pin not connected internally pin description 48 tsop logic symbol 16 q0-q15 a0-a19 acc ce oe we reset 20 a15 a14 a13 a12 a11 a10 a9 a8 nc nc we reset acc vcc a19 a18 a17 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 a16 v i/o gnd q15 q7 q14 q6 q13 q5 q12 q4 v cc q11 q3 q10 q2 q9 q1 q8 q0 oe gnd ce a0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 mx26l1620 44 sop 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 nc a18 a17 a7 a6 a5 a4 a3 a2 a1 a0 ce gnd oe q0 q8 q1 q9 q2 q10 q3 q11 nc a19 a8 a9 a10 a11 a12 a13 a14 a15 a16 we gnd q15 q7 q14 q6 q13 q5 q12 q4 vcc mx26l1620
4 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mx26l1620 flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15 a0-a19 ce oe we
5 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 automatic programming the mx26l1620 is word programmable using the auto- matic programming algorithm. the automatic program- ming algorithm makes the external system do not need to have time out sequence nor to verify the data pro- grammed. the typical chip programming time at room temperature of the mx26l1620 is less than 20 seconds. automatic programming algorithm mxic's automatic programming algorithm require the user to only write program set-up commands (including 2 un- lock write cycle and a0h) and a program command (pro- gram data and address). the device automatically times the programming pulse width, provides the program veri- fication, and counts the number of sequences. a status bit similar to data polling and a status bit toggling be- tween consecutive read cycles, provide feedback to the user as to the status of the programming operation. automatic chip erase the entire chip is bulk erased using 50 ms erase pulses according to mxic's automatic chip erase algorithm. typical erasure at room temperature is accomplished in less than 45 seconds. the automatic erase algorithm automatically programs the entire array prior to electrical erase. the timing and verification of electrical erase are controlled internally within the device. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stand- ard microprocessor write timings. the device will auto- matically pre-program and verify the entire array. then the device automatically times the erase pulse width, provides the erase verification, and counts the number of sequences. a status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the programming operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. all address are latched on the falling edge of we or ce, whichever happens later. all data are latched on the rising edge of we or ce, whichever happens later. mxic's flash technology combines years of eprom experience to produce the highest levels of quality, relia- bility, and cost effectiveness. the mx26l1620 electri- cally erases all bits simultaneously using fowler-nord- heim tunneling. the bytes are programmed by using the eprom programming mechanism of hot electron injec- tion. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.
6 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 operation ce oe we reset address q15~q0 read l l h h a in d out write(note 1) l h l h a in d in standby vcc 0.3v x x vcc 0.3v x high-z output disable l h h h x high-z reset x x x l x high-z legend: l=logic low=v il ,h=logic high=v ih ,v id =12.0 0.5v,x=don't care, a in =address in, d in =data in, d out =data out notes: 1. when the acc pin is at v hh , the device enters the accelerated program mode. see "accelerated program operations" for more information. table 1. bus operation(1) a5 a8 a14 operation ce oe we a0 a1 to a6 to a9 to a15~a21 q15~q0 a2 a7 a10 read silicon id l l h l l x l x v id x x00 c2h manufactures code read silicon id l l h h l x l x v id x x 22feh device code secured silscon xx88h sector indicator l l h h h x l x v id x x (factory locked) bit(q7) xx08h (non-factory locked) table 2. autoselect codes (high voltage method)
7 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 requirements for reading array data to read array data from the outputs, the system must drive the ce and oe pins to vil. ce is the power control and selects the device. oe is the output control and gates array data to the output pins. we should remain at vih. the internal state machine is set for reading array data upon device power-up, or after a hardware reset. this ensures that no spurious alteration of the memory contect occurs during the power transition. no command is necessary in this mode to obtain array data. standard microprocessor read cycles that assert valid address on the device address inputs produce valid data on the device data outputs. the device remains enabled for read access until the command register contents are altered. write commands/command sequences to program data to the device, the system must drive we and ce to vil, and oe to vih. an erase operation can erase the entire device. the "writing specific address and data commands or sequences into the command register initiates device operations. table 1 defines the valid register command sequences. writing incorrect address and data values or writing them in the improper sequence resets the device to reading array data."section has details on erasing the entire chip. after the system writes the autoselect command sequence, the device enters the autoselect mode. the system can then read autoselect codes from the internal reqister (which is separate from the memory array) on q15-q0. standard read cycle timings apply in this mode. refer to the autoselect mode and autoselect command sequence section for more information. icc2 in the dc characteristics table represents the active current specification for the write mode. the "ac characteristics" section contains timing specification table and timing diagrams for write operations. standby mode mx26l1620 can be set into standby mode with two dif- ferent approaches. one is using both ce and reset pins and the other one is using reset pin only. when using both pins of ce and reset, a cmos standby mode is achieved with both pins held at vcc 0.3v. under this condition, the current consumed is less than 50ua (typ.). if both of the ce and reset are held at vih, but not within the range of vcc 0.3v, the device will still be in the standby mode, but the standby currect will be larger. during auto algorithm operation, vcc ac- tive current (icc2) is required even ce = "h" until the operation is complated. the device can be read with stan- dard access time (tce) from either of these standby modes. when using only reset, a cmos standby mode is achieved with reset input held at vss 0.3v, under this condition the current is consumed less than 50ua (typ.). once the reset pin is taken high,the device is back to active without recovery delay. in the standby mode the outputs are in the high imped- ance state, independent of the oe input. mx26l1620 is capable to provide the automatic standby mode to restrain power consumption during read-out of data. this mode can be used effectively with an applica- tion requested low power consumption such as handy terminals. to active this mode, mx26l1620 automatically switch themselves to low power mode when mx26l1620 ad- dresses remain stable during access time of tacc+30ns. it is not necessary to control ce, we, and oe on the mode. under the mode, the current consumed is typi- cally 50ua (cmos level). output disable with the oe input at a logic high level (vih), output from the devices are disabled. this will cause the output pins to be in a high impedance state. reset operation the reset pin provides a hardware method of resetting the device to reading array data. when the reset pin is driven low for at least a period of trp, the device immediately terminates any operation in progress, tristates all output pins, and ignores all read/write commands for the duration of the reset pluse. the
8 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 device also resets the internal state machine to reading array data. the operation that was interrupted should be reinitated once the device is ready to accept another command sequence, to ensure data integrity current is reduced for the duration of the reset pulse. when reset is held at vss 0.3v, the device draws cmos standby current (icc4). if reset is held at vil but not within vss 0.3v, the standby current will be greater. the reset pin may be tied to system reset circuitry. a system reset would that also reset the mtp eprom. refer to the ac characteristics tables for reset parameters and to figure 14 for the timing diagram. silicon id read operation mtp eprom are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. eprom program- mers typically access signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design prac- tice. mx26l1620 provides hardware method to access the silicon id read operation. which method requires vid on a9 pin, vil on ce, oe, a6, and a1 pins. which apply vil on a0 pin, the device will output mxic's manufac- ture code of c2h. which apply vih on a0 pin, the device will output mx26l1620 device code of 22feh. vi/o pin operation mx26l1620 is capable to provide the i/o prower supply (vi/o) pin to control input/output voltage levels of the device. the data outputs and voltage tolerated at its data input is determined by the voltage on the vi/o pin. this device is allows to operate in 1.8v or 3v system as re- quired. data protection the mx26l1620 is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of spe- cific command sequences. the device also incorporates several features to prevent inadvertent write cycles re- sulting from vcc power-up and power-down transition or system noise. secured silicon sector the mx26l1620 features a flash memory region where the system may access through a command sequence to create a permant part identification as so called elec- tronic serial number (esn) in the device. once this re- gion is programmed, any further modification on the re- gion is impossible. the secured silicon sector is a 512 words in length, and uses a secured silicon sector indi- cator bit (q7) to indicate whether or not the secured silicon sector is locked when shipped from the factory. this bit is permanently set at the factory and cannot be changed, which prevent duplication of a factory locked part. this ensures the security of the esn once the prod- uct is shipped to the field. the mx26l1620 offers the device with secured silicon sector either factory locked or custor lockable. the fac- tory-locked version is always protected when shipped from the factory , and has the secured silicon sector indicator bit permanently set to a "1". the customer- lockable version is shipped with the secured silicon sector unprotected, allowing customer to utilize that sec- tor in any form they prefer. the customer-lockable ver- vcc / vi/o voltage range part no. vcc=2.7v to 3.6vvcc=2.7v to 3.6v vi/o=2.7v to 3.6vvi/o=1.65v to 2.6v mx26l1620-90 90ns 100ns mx26l1620-12 120ns 130ns table 3 notes: t ypical values measured at vcc=2.7v to 3.6v, vi/o=2.7v to 3.6v
9 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 sion has the secured sector indicator bit permanently set to a "0". therefore, the secured silicon sector indi- cator bit permanently set to a "0". therefore, the second silicon sector indicator bit prevents customer, lockable device from being used to replace devices that are fac- tory locked. the system access the secured silicon sector through a command sequence (refer to "enter secured silicon/ exit secured silicon sector command sequence). after the system has written the enter secured silicon sector command sequence, it may read the secured silicon sector by using the address normally occupied by the address 000000h-0001ffh. this mode of operation con- tinues until the system issues the exit secured silicon sector command sequence, or until power is removed from the device. on power-up, or following a hardware reset, the device reverts to sending command to ad- dress 000000h-0001fffh. low vcc write inhibit when vcc is less than vlko the device does not ac- cept any write cycles. this protects dataduring vcc power-up and power-down. the command register and all internal program/erase circuits are disabled, and the device resets. subsequent writes are ignored until vcc is greater thanvlko. the system must provide the proper signals to the control pins to prevent unintentional write when vcc is greater than vlko. write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power-up sequence the mx26l1620 powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command se- quences. factory locked:secured silicon sector programmed and protected at the factory in device with an esn, the secured silicon sector is protected when the device is shipped from the factory. the secured silicon sector cannot be modified in any way. a factory locked device has an 8-word random esn at address 000000h-000007h. customer lockable:secured silicon sector not programmed or protected at the factory as an alternative to the factory-locked version, the device may be ordered such that the customer may program and protect the 512-word secured silicon sector. programming and protecting the secured silicon sector must be used with caution since, once protected, there is no procedure available for unprotecting the secured silicon sector area and none of the bits in the secured silicon sector memory space can be modified in any way. the secured silicon sector area can be protected using the following procedures: write the three-cycle enter secured silicon sector region command sequence. this allows in-system protection of the secured silicon sector without raising any device pin to a high voltage. note that method is only applicable to the secured silicon sector. once the secured silicon sector is programmed, locked and verified, the system must write the exit secured silicon sector region command sequence to return to reading and writing the remainder of the array.
10 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data read(note 5) 1 ra rd reset(note 6) 1 xxx f0 autoselect(note 7) manufacturer id 4 555 aa 2aa 55 555 90 x00 c2 device id 4 555 aa 2aa 55 555 90 x01 22fe secured sector 4 555 aa 2aa 55 555 90 x03 see factory protect note9 enter secured silicon 3 555 aa 2aa 55 555 88 sector exit secured silicon 4 555 aa 2aa 55 555 90 xxx 00 sector porgram 4 555 aa 2aa 55 555 a0 pa pd chip erase 6 555 aa 2aa 55 555 80 555 aa 2aa 55 555 10 deep power down 3 555 aa 2aa 55 555 c0 software command defintions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 4 defines the valid register command sequences. either of the two reset command sequences will reset the device(when applicable). table4. mx26l1620 command definitions legend: x=don't care ra=address of the memory location to be read. rd=data read from location ra during read operation. pa=address of the memory location to be programmed. addresses are latched on the falling edge of the we or ce pulse. pd=data to be programmed at location pa. data is latched on the rising edge of we or ce pulse. all addresses are latched on the falling edge of we or ce, whichever happens later. all data are latched on ris- ing edge of we or ce, whichever happens first. notes: 1.see table 1 for descriptions of bus operations. 2.all values are in hexadecimal. 3.except when reading array or autoselect data, all bus cycles are write operation. 4.address bits are don't care for unlock and command cycles, except when pa is required. 5.no unlock or command cycles required when device is in read mode. 6.the reset command is required to return to the read mode when the device is in the autoselect mode or if q5 goes high. 7.the fourth cycle of the autoselect command sequence is a read cycle. 8.command is valid when device is ready to read array data or when device is in autoselect mode. 9.the data is 88h for factory locked and 08h for non-factory locked.
11 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 reading array data the device is automatically set to reading array data after device power-up. no commands are required to retrieve data. the device is also ready to read array data after completing an automatic program or automatic erase algorithm. the system must issue the reset command to re-en- able the device for reading array data if q5 goes high, or while in the autoselect mode. see the "reset command" section, next. reset command writing the reset command to the device resets the device to reading array data. address bits are don't care for this command. the reset command may be written between the se- quence cycles in an erase command sequence before erasing begins. this resets the device to reading array data. once erasure begins, however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in a program command sequence before programming begins. this resets the device to reading array data. once programming begins,however, the device ignores reset commands until the operation is complete. the reset command may be written between the se- quence cycles in an silicon id read command sequence. once in the silicon id read mode, the reset command must be written to return to reading array data. if q5 goes high during a program or erase operation, writing the reset command returns the device to reading array data. silicon id read command sequence the silicon id read command sequence allows the host system to access the manufacturer and devices codes, and determine whether or not. table 4 shows the address and data requirements. this method is an alternative to that shown in table 1, which is intended for eprom programmers and requires v id on address bit a9. the silicon id read command sequence is initiated by writing two unlock cycles, followed by the silicon id read command. the device then enters the silicon id read mode, and the system may read at any address any number of times, without init iating another command sequence. a read cycle at address xx00h retrieves the manufacturer code. a read cycle at address xx01h re- turns the device code. the system must write the reset command to exit the autoselect mode and return to reading array data. word program command sequence the command sequence requires four bus cycles, and is initiated by writing two unlock write cycles, followed by the program set-up command. the program address and data are written next, which in turn initiate the embedded program algorithm. the system is not required to provide further controls or timings. the device automatically generates the program pulses and verifies the programmed cell margin. table 4 shows the address and data requirements for the byte program command sequence. when the embedded program algorithm is complete, the device then returns to reading array data and addresses are no longer latched. the system can determine the status of the program operation by using q7, q6. see "write operation status" for information on these status bits. any commands written to the device during the em- bedded program algorithm are ignored. note that a hardware reset immediately terminates the programming operation. the word program command sequence should be reinitiated once the device has reset to reading array data, to ensure data integrity. programming is allowed in any sequence. a bit cannot be programmed from a "0" back to a "1". cause the data polling algorithm to indicate the operation was successful. however, a succeeding read will show that the data is still "0". only erase operations can convert a "0" to a "1". accelerated program operations the device offers accelerated program operations through the acc pin. when the system asserts v hh on the acc pin, the device automatically bypass the two "unlock" write cycle. the device uses the higher voltage on the acc pin to accelerate the operation. note that the acc pin must not be at v hh any operation other than accelerated programming, or device damage may result.
12 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 setup automatic chip erase chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cycles are then followed by the chip erase command 10h. the mx26l1620 contains a silicon-id-read operation to supplement traditional prom programming methodology. the operation is initiated by writing the read silicon id command sequence into the command register. follow- ing the command write, a read cycle with a6=vil, a1=vil, a0=vil retrieves the manufacturer code of c2h. a read cycle with a6=vil, a1=vil, a0=vih returns the device code of 22feh for mx26l1620. automatic chip erase command the device does not require the system to preprogram prior to erase. the automatic erase algorithm automati- cally preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. the system is not required to provide any controls or timings during these operations. table 4 shows the address and data requirements for the chip erase command sequence. any commands written to the chip during the automatic erase algorithm are ignored. note that a hardware reset during the chip erase operation immediately terminates the operation. the chip erase command sequence should be reinitiated once the device has returned to reading array data, to ensure data integrity. the system can determine the status of the erase op- eration by using q7, q6. see "write operation status" for information on these status bits. when the automatic erase algorithm is complete, the device returns to read- ing array data and addresses are no longer latched. figure 5 illustrates the algorithm for the erase opera- tion.see the erase/program operations tables in "ac characteristics" for parameters, and to figure 4 for tim- ing diagrams. table 5. silicon id code pins a0 a1 a6 q15 q7 q6 q5 q4 q3 q2 q1 q0 code(hex) | q8 manufacture code vil vil vil 00h 1 1 0 0 0010 00c2h device code for mx26l1620 vih vil vil 22h 1 1 1 1 1110 22feh table 6. write operation status notes: 1.performing successive read operations from any address will cause q6 to toggle. write operstion status the device provides several bits to determine the sta- tus of a write operation: q5, q6, q7. the following sub- sections describe the functions of these bits. q7, and status q7 q6 q5 note1 in progress word program in auto program algorithm q7 toggle 0 auto erase algorithm 0 toggle 0 exceeded word program in auto program algorithm q7 toggle 1 time limits auto erase algorithm 0 toggle 1 q6 each offer a method for determining whether a pro- gram or erase operation is complete or in progress. these three bits are discussed first.
13 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 q7: data polling the data polling bit, q7, indicates to the host sys-tem whether an automatic algorithm is in progress or com- pleted. data polling is valid after the rising edge of the final we pulse in the program or erase command se- quence. during the automatic program algorithm, the device out- puts on q7 the complement of the datum programmed to q7. this q7 status also applies to programming dur- ing er ase suspend. when the automatic program algo- rithm is complete, the device outputs the datum pro- grammed to q7. the system must provide the program address to read valid status information on q7. during the automatic erase algorithm, data polling pro- duces a "0" on q7. when the automatic erase algorithm is complete. data polling produces a "1" on q7. this is analogous to the complement/true datum out-put de- scribed for the automatic program algorithm: the erase function changes all the bits to "1" prior to this, the de- vice outputs the "complement, or "0". q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete. toggle bit i may be read at any address, and is valid after the rising edge of the final we or ce, whichever happens first pulse in the command sequence(prior to the pro- gram or erase operation). during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe or ce to con- trol the read cycles. when the operation is complete, q6 stops toggling. q5:program/erase timing q5 will indicate if the program or erase time has exceeded the specified limits(internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not suc- cessfully completed. data polling and toggle bit are the only operating functions of the device under this condi- tion. if this time-out condition occurs during sector erase op- eration, it specifies that a is bad and it may not be re- used. write the reset command sequence to the de- vice, and then execute program or erase command se- quence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad. if this time-out condition occurs during the word program- ming operation, the word is bad and maynot be reused, (other word are still functional and can be reused).
14 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . ..... -65 o c to +150 o c ambient temperature with power applied. . . . . . . . . . . . . .... -65 o c to +125 o c voltage with respect to ground vcc (note 1) . . . . . . . . . . . . . . . . . -0.5 v to +4.0 v a9, oe, and reset (note 2) . . . . . . . . . . . ....-0.5 v to +12.5 v all other pins (note 1) . . . . . . . -0.5 v to vcc +0.5 v output short circuit current (note 3) . . . . . . 200 ma notes: 1. minimum dc voltage on input or i/o pins is -0.5 v. during voltage transitions, input or i/o pins may over- shoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc voltage on input or i/o pins is vcc +0.5 v. during voltage transitions, input or i/o pins may overshoot to vcc +2.0 v for periods up to 20 ns. see figure 7. 2. minimum dc input voltage on pins a9, oe, and reset is -0.5 v. during voltage transitions, a9, oe, and reset may overshoot vss to -2.0 v for periods of up to 20 ns. see figure 6. maximum dc input volt- age on pin a9 is +12.5 v which may overshoot to 14.0 v for periods up to 20 ns. 3. no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. stresses above those listed under "absolute maximum rat-ings" may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those in- dicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maxi- mum rating conditions for extended periods may affect device reliability. operating ratings commercial (c) devices ambient temperature (t a ). . . . . . . . . . . . 0 c to +70 c industrial (i) devices ambient temperature (t a ). . . . . . . . . . -40 c to +85 c v cc supply voltages v cc for full voltage range. . . . . . . . . . . +2.7 v to 3.6 v operating ranges define those limits between which the functionality of the device is guaranteed.
15 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 para- vi/o=2.7v~3.6v vi/o=1.65v~2.6v meter description test conditions min typ max min typ max unit i li input load current (note 1) vin = vss to vcc , 1.0 1.0 ua vcc = vcc max i lit a9 input load current vcc=vcc max; a9 = 12.5v 35 35 ua i lo output leakage current vout = vss to vcc , 1.0 1.0 ua vcc= vcc max icc1 vcc active read current ce= vil, oe = vih 5 mhz 9 16 9 16 ma (notes1, 2) 1 mhz 2 4 2 4 ma icc2 vcc active write current ce= v il , oe = v ih 26 30 26 30 ma (notes 1, 3, 4) icc3 vcc standby current (cmos) ce,reset, 30 100 30 100 ua (note 1) acc=vcc 0.3v icc4 vcc standby current (ttl) ce=vih 0.5 1 0.5 1 ma (note 1) icc5 vcc reset current (note 1) reset = v ss 0.3 v, 0.2 5 0.2 5 ua acc = vcc 0.3 v iacc acc accelerated program ce=vil, oe=vih acc pin 5 10 5 10 ma current, word vcc pin 15 30 15 30 ma vil input low voltage -0.5 0.8 0.4 v vih input high voltage 0.7xvcc vcc+0.3 vi/o-0.4 v vhh voltage for acc vcc = 3.0 v 10% 8.5 9.5 8.5 9.5 v program acceleration vid voltage for autoselect vcc = 3.0 v 10% 11.5 12.5 11.5 12.5 v vol output low voltage iol= 4.0ma,vcc=vcc min 0.45 0.45 v voh1 output high voltage ioh=-2.0ma,vcc=vcc min 0.85vi/o 0.85vi/o v voh2 ioh=-100ua,vcc=vcc min vi/o-0.4 vi/o-0.4 v vlko low v cc lock-out voltage 2.3 2.5 2.3 2.5 v (note 4) notes: 1. maximum icc specifications are tested with vcc = vcc max. 2. the icc current listed is typically is less than 2 ma/mhz, with oe at v ih . typical specifications are for vcc = 3.0 v. 3. icc active while embedded erase or embedded program is in progress. 4. not 100% tested. dc characteristics ta=0 c to 70 c, vcc=2.7v~3.6v
16 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 switching test circuits wavefrom inputs outputs steady changing from h to l changing from l to h don't care, any change permitted changing, state unknown does not apply center line is high impedance state(high z) key to switching waveforms switching test waveforms test specifications test condition 90 120 unit output load 1 ttl gate output load capacitance, cl 30 100 pf (including jig capacitance) input rise and fall times 5 ns input pulse levels 0.0-3.0 v input timing measurement 1.5 v reference levels output timing measurement 1.5 v reference levels device under test diodes=in3064 or equivalent cl 6.2k ohm 2.7k ohm 3.3v 1.5v vio/2 measurement level 3.0v 0.0v output input
17 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 symbol description condition 90 120 unit tacc address to output delay ce=vil max 90 120 ns oe=vil tce chip enable to output delay oe=vil max 90 120 ns toe output enable to output delay max 34 44 ns tdf oe high to output float(note1) max 25 35 ns toh output hold time of from the rising edge of min 0 0 ns address, ce, or oe, whichever happens first trc read cycle time (note 1) min 90 120 ns twc write cycle time (note 1) min 90 120 ns tcwc command write cycle time(note 1) min 90 120 ns tas address setup time min 0 0 ns tah address hold time min 45 50 ns tds data setup time min 45 50 ns tdh data hold time min 0 0 ns tvcs vcc setup time(note 1) min 50 50 us tcs chip enable setup time min 0 0 ns tch chip enable hold time min 0 0 ns toes output enable setup time (note 1) min 0 0 ns toeh output enable hold time (note 1) read min 0 0 ns toggle & min 10 10 ns data polling twes we setup time min 0 0 ns tweh we hold time min 0 0 ns tcep ce pulse width min 45 50 ns tceph ce pulse width high min 30 30 ns twp we pulse width min 35 50 ns twph we pulse width high min 30 30 ns tolz output enable to output low z max 30 40 ns twhgl we high to oe going low min 30 30 ns note: 1.not 100% tested 2.t r = t f = 5ns ac characteristics ta=0 c to 70 c, vcc=2.7v~3.6v
18 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 1. command write operation addresses ce oe we din tds tah data tdh tcs tch tcwc twph twp toes tas vcc 5v vih vil vih vil vih vil vih vil vih vil add valid read/reset operation fig 2. read timing waveforms addresses ce oe tacc we vih vil vih vil vih vil vih vil voh vol high z high z data valid toe tolz toeh tdf tce trc outputs toh add valid
19 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 3. reset timing wavform ac characteristics parameter description test setup all speed options unit tready reset pin low (not during automatic max 500 ns algorithms) to read or write (see note) trp1 reset pulse width (during automatic algorithms) min 10 us trp2 reset pulse width (not during automatic algorithms) min 500 ns trh reset high time before read(see note) min 50 ns note:not 100% tested trh trp2 trp1 tready ce, oe reset reset timing not during automatic algorithms reset timing during automatic algorithms reset
20 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 erase/program operation fig 4. automatic chip erase timing waveform twc address oe ce 55h 2aah 555h 10h in progress complete va va tas tah tghwl tch twhgl twp tds tdh twhwh2 read status data erase command sequence(last two cycle) tcs twph tvcs we data vcc
21 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes write data 10h address 555h write data 55h address 2aah data = ffh ? yes auto erase completed data poll from system no
22 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 6. automatic program timing waveforms fig 7. accelerated program timing diagram acc tvhh vhh (8.5v ~ 9.5v) vil or vih vil or vih tvhh twc address oe ce a0h 555h pa pd status dout pa pa notes: 1.pa=program address, pd=program data, dout is the true data the program address tas tah tghwl tch twp tds tdh twhwh1 read status data (last two cycle) program command sequence(last two cycle) twhgl tcs twph tvcs we data vcc
23 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 8. ce controlled program timing waveform twc twh tghel twhwh1 or 2 tcp address we oe ce data q7 pa data polling dout reset notes: 1.pa=program address, pd=program data, dout=data out, q7=complement of data written to device. 2.figure indicates the last two bus cycles of the command sequence. tah tas pa for program 555 for chip erase twhgl trh tdh tds tws a0 for program 55 for erase tcph tbusy pd for program 10 for chip erase 555 for program 2aa for erase
24 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 9. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes verify word ok ? yes auto program completed data polling from system increment address last address ? no no
25 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 10. secured silicon sector protected alogorithms flowchart start enter secured silicon sector wait 1us second wait cycle data=60h a6=0, a1=1, a0=0 frist wait cycle data=60h yes no data=01h? wait 300us write reset command device failed secured sector protect complete
26 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 11. silicon id read timing waveform tacc tce tacc toe toh toh tdf data out 00c2h 22fe vid vih vil add a9 add ce a1 oe we add a0 data out data q0-q15 vcc 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil
27 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 write operation status fig 12. data polling timing waveforms (during automatic algorithms) notes: va=valid address. figure shows are first status cycle after command sequence, last status read cycle, and array data read cycle . tdf tce tacc trc tch toe toeh toh address ce oe we dq7 q0-q6 status data status data complement complement valid data tr u e va va va high z high z valid data tr u e
28 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 13. data polling algorithm start read q7~q0 add. = va (1) ye s ye s ye s no no no q7 = data ? q7 = data ? q5 = 1 ? read q7~q0 add. = va pass fail (2) notes: 1.va=valid address for programming. 2.q7 should be rechecked even q5="1"because q7 may change simultaneously with q5.
29 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 fig 14. toggle bit timing waveforms (during automatic alogrithms) notes: va=valid address; not required for q6. figure shows first two status cycle after command sequence, last status read cycle, and array data read cycle. tdf tce tacc trc tch toe toeh high z toh address ce oe we q6/q2 valid status (first raed) valid status (second read) (stops toggling) valid data va va va va valid data
30 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 start read q7~q0 read q7~q0 yes no toggle bit q6 =toggle? q5=1? yes no (note 1) read q7~q0 twice (note 1,2) toggle bit q6= toggle? program/erase operation not complete, write reset command yes program/erase operation complete fig 15. toggle bit algorithm note: 1.read toggle bit twice to determine whether or not it is toggling. 2.recheck toggle bit because it may stop toggling as q5 changes to "1".
31 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time. limits parameter min. typ.(2) max. units chip erase time 45 450 sec word programming time 30 350 us chip programming time 35 75 sec accelerated word program time 7 210 us erase/program cycles 100 cycles latchup characteristics erase and programming performance(1) note: 1.not 100% tested, excludes external system level over head. 2.typical values measured at 25 c,3.3v. additionally programming typicals assume checkerboard pattern. parameter symbol parameter description test set typ max unit cin input capacitance vin=0 6 7.5 pf cout output capacitance vout=0 8.5 12 pf cin2 control pin capacitance vin=0 7.5 9 pf capacitance ta=0 c to 70 c, vcc=2.7v~3.6v notes: 1. sampled, not 100% tested. 2. test conditions ta=25 c, f=1.0mhz parameter test conditions min unit minimum pattern data retention time 150 10 years 125 20 years data retention
32 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 ordering information plastic package part no. access time tem perature package type ball pitch (ns) range mx26l1620mc-90 90 commerical 44 pin sop - mx26l1620mc-12 120 commerical 44 pin sop - mx26l1620tc-90 90 commerical 48 pin tsop - (normal type) mx26l1620tc-12 120 commerical 48 pin tsop - (normal type) mx26l1620xac-90 90 commerical 48 ball csp 0.75 mm mx26l1620xac-12 120 commerical 48 ball csp 0.75 mm mx26l1620xbc-90 90 commerical 48 ball csp 0.8 mm mx26l1620xbc-12 120 commerical 48 ball csp 0.8 mm mx26l1620mi-90 90 industrial 44 pin sop - mx26l1620mi-12 120 industrial 44 pin sop - mx26l1620ti-90 90 industrial 48 pin tsop - (normal type) mx26l1620ti-12 120 industrial 48 pin tsop - (normal type) mx26l1620xai-90 90 industrial 48 ball csp 0.75 mm MX26L1620XAI-12 120 industrial 48 ball csp 0.75 mm mx26l1620xbi-90 90 industrial 48 ball csp 0.8 mm mx26l1620xbi-12 120 industrial 48 ball csp 0.8 mm
33 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 48-pin plastic tsop package information
34 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 44-pin sop
35 p/n:pm0827 rev. 0.4, jan. 31, 2002 mx26l1620 revision history revision no. description page date 0.1 1.to added the vi/o voltage range and performance p1,7 jul/23/2001 2.to modify autoselect code table p5 3.to added deep power-down mode p9,10 4.to added chip erase algorithm flowchart p23 5.to added secured silicon sector protect algorithm flowchart p24 6.to modify the 14-pin of 48 tsop package from nc to vcc p2 0.2 1.to added 44 sop package p1,2,34 jul/31/2001 2.to modify the vi/o range from 1.8v~5v to 1.8v~3.6v p1 3.cancel th regulated voltage range 14 4.modify dc characteristics table for vil/vih voltage when vi/o range p15 is 1.8v~2.6v 0.3 1.to modify vi/o voltage range from 1.8v to 1.65v p1,8,15 sep/26/2001 2.to modify icc4/tcs/tch/tolz/twhgl spec p14,17 3.to modify vcc standby current from 50ua to 30ua p1,15 4.cancel the deep power down mode p11,15 5.to modify programming time p31 0.4 1.to modify the content error p1,7,11 jan/31/2002 2.to modify fast erase time:23s/chip (typ.)-->45s/chip(typ.) p1,5,31
mx26l1620 m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

▲Up To Search▲

Price & Availability of MX26L1620XAI-12

	To Download MX26L1620XAI-12 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .